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RK3399高速信号 PCB 设计建议 Crystal晶振设计指南 – 吴川斌的博客
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RK3399高速信号 PCB 设计建议 Crystal晶振设计指南

RK3399高速信号 PCB 设计建议 Crystal晶振设计指南

RK3399高速信号 PCB 设计建议–Crystal晶振设计, 在时钟电路的PCB设计中,请注意:

  • 在布局时,晶体电路尽可能地靠近RK3399的时钟管脚放置;
  • 信号走线使用4mil走线,并且尽可能的短,以减少走线的负载电容和防止不必要的噪声;
  • 时钟走线Xin和Xout以及晶体下方投影区域禁止任何走线,避免噪声耦合进入时钟电路;
  • 晶体下方的顶层,可以围绕放置地环。地环通过过孔与相邻的接地层连接,以隔离噪声;
  • 晶体下方的第二层保持完整的地参考平面,避免任何走线分割,有助于隔离噪声保持晶体输出的稳定性;
  • Y29做为晶体的模拟地,在layout时请注意与其他的数字地隔离,并单独通过过孔连接到第二层的地参考平面;

 

 

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2 Comments

  • 追曦荫泉 says:
    2017年9月5日 at 上午10:45

    请问这个文章里配的电路是用哪个软件画的？感觉界面好看多。

    • says:
      2017年9月6日 at 上午9:23

      原理图：OrCAD PCB：Allegro 仿真：SIWAVE

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